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Features
* 32-Mbit Flash and 4-Mbit/8-Mbit SRAM * Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package * 2.7V to 3.3V Operating Voltage
Flash
* 2.7V to 3.3V Read/Write * Access Time - 70 ns * Sector Erase Architecture * * *
- Sixty-three 32K WordSectors with Individual Write Lockout - Eight 4K Word Sectors with Individual Write Lockout Fast Word Program Time - 15 s Sector Erase Time - 300 ms Suspend/Resume Feature for Erase and Program - Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 12 mA Active - 13 A Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection VPP Pin for Write Protection and Accelerated Program/Erase Operations RESET Input for Device Initialization Sector Lockdown Support Top or Bottom Boot Block Configuration Available 128-bit Protection Register Minimum 100,000 Erase Cycles
* * * * * * * *
32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory AT52BR3224A AT52BR3224AT AT52BR3228A AT52BR3228AT
SRAM
* * * * * *
4-megabit (256K x 16)/8-megabit (512K x 16) 2.7V to 3.3V VCC 70 ns Access Time Fully Static Operation and Tri-state Output 1.2V (Min) Data Retention Industrial Temperature Range
Device Number AT52BR3224A AT52BR3224AT AT52BR3228A AT52BR3228AT
Flash Boot Location Bottom Top Bottom Top
Flash Plane Architecture 32M 32M 32M 32M
SRAM Configuration 256K x 16 256K x 16 512K x 16 512K x 16
Preliminary
Rev. 3338B-STKD-6/03
1
Pin Configuration
Pin Name A0 - A17 A0 - A18 A19 - A20 CE OE WE RESET RDY/BUSY VPP VCC GND I/O0 - I/O15 NC SLB SUB SVCC SGND SCS1 SCS2 SWE SOE Function Flash/SRAM Common Address Input for 4M SRAM Flash/SRAM Common Address Input for 8M SRAM Flash Address Input Flash Chip Enable Flash Output Enable Flash Write Enablee Flash Reset Flash READY/BUSY Output Flash Power Supply for Accelerated Program/Erase Operations Flash Power Flash Ground Data Inputs/Outputs No Connect SRAM Lower Byte SRAM Upper Byte SRAM Power SRAM Ground SRAM Chip Select 1 SRAM Chip Select 2 SRAM Write Enable SRAM Output Enable
AT52BR3224A(T)/ AT52BR3228A(T) (Top View)
A B
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
A20 A16
A11 A8
A15 A10
A14 A9
A13
A12
GND
NC I/O7 I/O5
NC
NC
I/O15 SWE I/O14 I/O13 I/O6 I/O4
C
WE RDY/BUSY
D
SGND RES I/O12 SCS2 SVCC VCC A19 SOE A7 A4 A6 A0 I/O11 I/O9 A3 CE I/O10 I/O8 A2 GND I/O2 I/O0 A1 OE I/O3 I/O1 SCS1 NC NC NC
E
NC VPP SUB A17 A5
F
SLB
G
A18
H
NC NC NC
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Block Diagram
ADDRESS OE WE SOE SWE
RESET CE RDY/BUSY
32-Mbit FLASH
4/8-Mbit SRAM
SCS1 SCS2
DATA
Description
The AT52BR3224A(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM (organized as 256K x 16) in a stacked 66-ball CBGA package. The AT52BR3228A(T) combines a 32-megabit Flash (2M x 16) and an 8-megabit SRAM (organized as 512K x 16) in a stacked 66-ball CBGA package. The stacked modules operate at 2.7V to 3.3V in the industrial temperature range.
Absolute Maximum Ratings
Temperature under Bias.................................. -40 C to +85 C Storage Temperature .................................... -55 C to +150 C All Input Voltages except VPP and RESET (including NC Pins) with Respect to Ground .....................................-0.2V to +3.3V Voltage on VPP with Respect to Ground ..................................-0.2V to + 6.25V Voltage on RESET with Respect to Ground ...................................-0.2V to +13.5V All Output Voltages with Respect to Ground .....................................-0.2V to +0.2V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC Operating Range
AT52BR3224A(T)/3228A(T)-70 Operating Temperature (Case) VCC Power Supply Industrial -40 C - 85 C 2.7V to 3.3V
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32-megabit Flash Memory Description
The 32-megabit Flash is a a 2.7-volt memory organized as 2,097,152 words of 16 bits each. The memory is divided into 71 sectors for erase operations. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see "Sector Lockdown" section). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit. The VPP pin provides data protection. When the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase operations can be performed. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code.
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Block Diagram
I/O0 - I/O15
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
A0 - A20
INPUT BUFFER
STATUS REGISTER
DATA REGISTER
IDENTIFIER REGISTER
COMMAND REGISTER
ADDRESS LATCH DATA COMPARATOR
CE WE OE RESET
RDY/BUSY WRITE STATE MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE VOLTAGE SWITCH
VPP
VCC GND X-DECODER
MAIN MEMORY
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Device Operation
READ: The 32-Mbit Flash memory is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the "Command Definition in Hex" table on page 14 (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71 sectors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating immediately. WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0") on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses.
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AT52BR3224A(T)/3228A(T)
Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a "1", the device was not able to verify that the erase or program operation was performed successfully. VPP PIN: The circuitry of the 32-Mbit Flash is designed so that the device cannot be programmed or erased if the VPP voltage is less that 0.4V. When VPP is at 0.9V or above, normal program and erase operations can be performed. The VPP pin cannot be left floating. PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The "Status Bit Table" on page 13 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the device contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, "00" or "01". If the configuration register is set to "00", the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a "01", a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a "00" or to a "01", any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is "00". Using the four-bus cycle Set Configuration Register command as shown in the "Command Definition in Hex" table on page 14, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below. DATA POLLING: The device features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a "00", during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see "Status Bit Table" on page 13 for more details. If the status bit configuration register is set to a "01", the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 1 and 2 on page 11.
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TOGGLE BIT: In addition to Data Polling the device provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see "Status Bit Table" on page 13 for more details. The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 3 and 4 on page 12. ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a "1", the device is unable to verify that an erase or a word program operation has been successfully performed. If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a "0" while the erase or program operation is still in progress. Please see "Status Bit Table" on page 13 for more details. V PP STATUS BIT: The device provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a "1". Once the VPP status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status bit will output a "0". Please see "Status Bit Table" on page 13 for more details. SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector's usage as a write-protected region is optional to the user. At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see "Software Product Identification Entry/Exit" sections on page 27), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation.
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AT52BR3224A(T)/3228A(T)
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 20 s to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other word within the device that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see "Operating Modes" on page 20 (for hardware operation) or "Software Product Identification Entry/Exit" sections on page 27. The manufacturer and device codes are the same for both modes. 128-BIT PROTECTION REGISTER: The device contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the "Command Definition in Hex" table on page 14. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the "Command Definition in Hex" table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the "Protection Register Addressing Table" on page 15 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation.
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RDY/BUSY: For the 32-Mbit Flash memory, an open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. Please see "Status Bit Table" on page 13 for more details. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the device in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit: VPP is less than VILPP. (e) VPP power-on delay: once VPP has reached 1.65V, program and erase operations are inhibited for 100 ns. INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V. OUTPUT LEVELS: For the device, output high levels (VOH) are equal to VCCQ - 0.2V (not VCC). For 2.7V - 3.6V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output levels, VCCQ must be regulated to 2.0V 10%, while VCC must be regulated to 2.7V - 3.0V (for minimum power).
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Figure 1. Data Polling Algorithm (Configuration Register = 00) Figure 2. Data Polling Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0 Addr = VA
Read I/O7 - I/O0
YES I/O7 = Data?
Toggle Bit = Toggle? NO
NO
YES
NO
I/O3, I/O5 = 1?
NO
I/O3, I/O5 = 1?
YES Read I/O7 - I/O0 Addr = VA
YES Read I/O7 - I/O0 Twice
I/O7 = Data?
YES
Toggle Bit = Toggle? YES
NO
NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode
Note: Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5.
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.
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Figure 3. Toggle Bit Algorithm (Configuration Register = 00)
Figure 4. Toggle Bit Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
YES Read I/O7 - I/O0 Twice
YES Read I/O7 - I/O0 Twice
Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command
NO
Toggle Bit = Toggle? YES
NO
Program/Erase Operation Successful
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful, Write Product ID Exit Command
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
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AT52BR3224A(T)/3228A(T)
Status Bit Table
Status Bit I/O7 Configuration Register Programming Erasing Erase Suspended & Read Erasing Sector Erase Suspended & Read Non-erasing Sector Erase Suspended & Program Non-erasing Sector Notes: 00 I/O7 0 1 DATA I/O7 I/O7 01 0 0 1 DATA 0 I/O6 00/01 TOGGLE TOGGLE 1 DATA TOGGLE I/O5(1) 00/01 0 0 0 DATA 0 I/O3(2) 00/01 0 0 0 DATA 0 I/O2 00/01 1 TOGGLE TOGGLE DATA TOGGLE RDY/BUSY 00/01 0 0 1 1 0
1. I/O5 switches to a "1" when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a "1" when the VPP level is not high enough to successfully perform program and erase operations.
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Command Definition in Hex(1)
Command Sequence Read Chip Erase Sector Erase Word Program Enter Single Pulse Program Mode Single Pulse Word Program Sector Lockdown Erase/Program Suspend Erase/Program Resume Product ID Entry Product ID Exit(5) Product ID Exit(5) Program Protection Register Lock Protection Register - Block B Status of Block B Protection Set Configuration Register Bus Cycles 1 6 6 4 6 1 6 1 1 3 3 1 4 4 4 4 1st Bus Cycle Addr Addr 555 555 555 555 Addr 555 XXX XXX 555 555 XXX 555 555 555 555 Data DOUT AA AA AA AA DIN AA B0 30 AA AA F0(8) AA AA AA AA AAA AAA AAA AAA 55 55 55 55 555 555 555 555 C0 C0 90 D0 Addr 080 80 XXX DIN X0 DOUT(6) 00/01(7) AAA AAA 55 55 555 555 90 F0(8) AAA(2) 55 555 80 555 AA AAA 55 SA(3)(4) 60 AAA(2) AAA AAA AAA 55 55 55 55 555 555 555 555 80 80 A0 80 555 555 Addr 555 AA AA DIN AA AAA 55 555 A0 AAA AAA 55 55 555 SA(3)(4) 10 30 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data Addr 4th Bus Cycle Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data
Notes:
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are don't care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are don't care in the word mode. 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 18-17 for details). 4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. Either one of the Product ID Exit commands can be used. 6. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed. 7. The default state (after power-up) of the configuration register is "00". 8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
Absolute Maximum Ratings*
Temperature under Bias................................. -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .................................. -0.6V to +6.25V All Output Voltages with Respect to Ground ............................ -0.6V to VCC + 0.6V Voltage on VPP with Respect to Ground .................................. -0.6V to +13.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT52BR3224A(T)/3228A(T)
Protection Register Addressing Table
Word 0 1 2 3 4 5 6 7 Note: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
All address lines not specified in the above table must be "0" when accessing the protection register, i.e., A20 - A8 = 0.
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Bottom Boot - Sector Address Table
x16 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 Address Range (A20 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF
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AT52BR3224A(T)/3228A(T)
Bottom Boot - Sector Address Table (Continued)
x16 Sector SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Address Range (A20 - A0) F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 -1F7FFF 1F8000 - 1FFFF
17
3338B-STKD-6/03
Top Boot - Sector Address Table
x16 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Address Range (A20 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF
SA35 SA36
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AT52BR3224A(T)/3228A(T)
3338B-STKD-6/03
AT52BR3224A(T)/3228A(T)
Top Boot - Sector Address Table (Continued)
x16 Sector SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Address Range (A20 - A0) 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1F8FFF 1F9000 - 1F9FFF 1FA000 - 1FAFFF 1FB000 - 1FBFFF 1FC000 - 1FCFFF 1FD000 - 1FDFFF 1FE000 - 1FEFFF 1FF000 - 1FFFFF
19
3338B-STKD-6/03
DC and AC Operating Range
32-Mbit Flash Operating Temperature (Case) VCC Power Supply Ind. -40C - 85C 2.7V to 3.6V
Operating Modes
Mode Read Program/Erase
(2)
CE VIL VIL VIH X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X X X
RESET VIH VIH VIH VIH VIH VIH VIH VIL
VPP X VIHPP X X X VILPP(7) X X
(6)
Ai Ai Ai X
I/O DOUT DIN High-Z
Standby/Program Inhibit
X VIL X VIH X
Program Inhibit
X X
Output Disable Reset Product Identification Hardware
X X
High-Z X High-Z
VIL
VIL
VIH
VIH
A1 - A20 = VIL, A9 = VH(3), A0 = VIL A1 - A20 = VIL, A9 = VH(3), A0 = VIH A0 = VIL, A1 - A20 = VIL A0 = VIH, A1 - A20 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
VIH
Notes:
1. 2. 3. 4. 5. 6. 7.
X can be VIL or VIH. Refer to AC programming waveforms on page 25. VH = 12.0V 0.5V. Manufacturer Code: 001FH (x16), Device Code: 00C8H (x16)-Bottom Boot; 00C9H (x16)-Top Boot. See details under "Software Product Identification Entry/Exit" on page 27. VIHPP (min) = 0.9V; VIHPP (max) = 3.6V. VILPP (max) = 0.4V.
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AT52BR3224A(T)/3228A(T)
3338B-STKD-6/03
AT52BR3224A(T)/3228A(T)
DC Characteristics
Symbol ILI ILO ISB ICC(1) ICC1 IPP1 VIL VIH VOL1 VOL2 VOH1 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Read Current VCC Programming Current VPP Input Load Current Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage IOL = 2.1 mA IOL = 1.0 mA IOH = -400 A Output High Voltage IOH = -400 A IOH = -400 A IOH = -100 A VOH2 Output High Voltage IOH = -100 A IOH = -100 A VCCQ < 2.6V VCCQ 2.6V VCCQ < 2.6V VCCQ 2.6V VCCQ - 0.2 2.4 2.4 VCCQ - 0.1 2.5 2.5 2.0 0.45 0.20 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC f = 5 MHz; IOUT = 0 mA 13 12 Min Typ Max 10 10 25 25 45 10 0.6 Units A A A mA mA A V V V V V V V V V V
Note:
1. In the erase mode, ICC is 65 mA.
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3338B-STKD-6/03
AC Read Characteristics
32-Mbit Flash Symbol tRC tACC tCE(1) tOE(2) tDF(3)(4) tOH tRO Parameter Read Cycle Time Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first RESET to Output Delay 0 0 0 100 Min Max 70 70 70 40 25 Units ns ns ns ns ns ns ns
AC Read Waveforms(1)(2)(3)(4)
tRC ADDRESS ADDRESS VALID
CE
tCE OE tOE tDF tACC tOH
RESET HIGH Z
tRO OUTPUT VALID
OUTPUT
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
Note:
This parameter is characterized and is not 100% tested.
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3338B-STKD-6/03
AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High Min 0 35 0 0 35 35 0 35 Max Units ns ns ns ns ns ns ns ns
AC Word Load Waveforms
WE Controlled
CE Controlled
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AT52BR3224A(T)/3228A(T)
3338B-STKD-6/03
AT52BR3224A(T)/3228A(T)
Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tWC tRP tEC tSEC1 tSEC2 tES tPS Parameter Word Programming Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Write Cycle Time Reset Pulse Width Chip Erase Cycle Time Sector Erase Cycle Time (4K Word Sectors) Sector Erase Cycle Time (32K Word Sectors) Erase Suspend Time Program Suspend Time 0 35 35 0 35 35 70 500 80 0.3 1.2 400 3.0 5.0 15 20 Min Typ 15 Max 150 Units s ns ns ns ns ns ns ns ns seconds seconds seconds s s
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tWPH tBP
WE
tAS tAH
555 AAA
tDH
555 ADDRESS 555
A0 - A20
tWC
tDS
AA 55 A0 INPUT DATA AA
DATA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP tWPH
WE
tAS tAH
555 AAA
tDH
555 555 AAA Note 2
A0-A20
tWC
tDS
AA 55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 Note 3 WORD 5
tEC
DATA
WORD 0
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under "Command Definitions in Hex" on page 14.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
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3338B-STKD-6/03
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 22.
0
ns
Data Polling Waveforms
WE CE OE tDH I/O7 A0-A20 An tOEH tOE HIGH Z An An An An tWR
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 22.
(2)
Min 10 10
Typ
Max
Units ns ns ns
50 0
ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 90 TO ADDRESS 555
LOAD DATA 80 TO ADDRESS 555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 555
Software Product Identification Exit(1)(6)
LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA 60 TO SECTOR ADDRESS
PAUSE 200 s(2)
LOAD DATA F0 TO ADDRESS 555
Notes:
EXIT PRODUCT IDENTIFICATION MODE(4)
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A20 (Don't Care). 2. Sector Lockdown feature enabled.
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), and A11 - A20 (Don't Care). 2. A1 - A20 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH(x16) Device Code: 00C8 (x16)-Bottom Boot 00C9H (x16)-Top Boot. 6. Either one of the Product ID Exit commands can be used.
27
3338B-STKD-6/03
4-megabit SRAM Description Features
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for high-speed and low-power circuit technology. It is particularly well-suited for the high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
* Fully Static Operation and Tri-state Output * TTL Compatible Inputs and Outputs * Battery Backup
- 1.2V (Min) Data Retention
Voltage (V) 2.7 - 3.3
Speed (ns) 70
Operation Current/ICC (mA) (Max) 3
Standby Current (A) (Max) 10
Temperature ( C) -40 - 85
Block Diagram
A0 ROW DECODER SENSE AMP I/O0
DATA I/O BUFFER
BLOCK DECODER
PRE DECODER
ADD INPUT BUFFER
I/O7 I/O8
MEMORY ARRAY 256K X 16 WRITE DRIVER
COLUMN DECODER
I/O15
A17
SCS1 SCS2 SOE SLB SUB SWE
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Absolute Maximum Ratings(1)
Symbol VIN, VOUT VCC TA TSTG PD Note: Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Rating -0.3 to 3.6 -0.3 to 4.6 -40 to 85 -55 to 150 1.0 Unit V V C C W
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Truth Table
I/O Pin SCS1 H(1) X
(1)
SCS2 X
SWE
SOE
SLB(2) X
SUB(2) X
Mode
I/O0 - I/O7
I/O8 - I/O15
Power
L X
X
X H L H H L L H L
Deselected
High-Z
High-Z
Standby
X
L
(1)
H
H
H
H L L H
Output Disabled
High-Z
High-Z
Active
DIN High-Z Write DIN DIN
High-Z DIN DIN High-Z High-Z DOUT DOUT High-Z Active Active
L
H
L
X L L H L H L
DOUT High-Z Read DOUT DOUT
L
H
H
L L L
Notes:
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH) 2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8 - I/O15.
Recommended DC Operating Condition
Symbol VCC VSS VIH VIL
(1)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage
Min 2.7 0 2.2 -0.3
(1)
Typ 3.0 0
Max 3.3 0 VCC + 0.3 0.6
Unit V V V V
Note:
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
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3338B-STKD-6/03
DC Electrical Characteristics
TA = -40 C to 85 C
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition VSS < VIN < VCC VSS < VOUT < VCC, SCS1 = VIH or SCS2=VIL or SOE = VIH or SWE = VIL or SUB = VIH, SLB = VIH SCS1 = VIL, SCS2=VIH, VIN = VIH or VIL, II/O = 0 mA SCS1 = VIL, SCS2 = VIH, VIN = VIH or VIL, Cycle Time = Min 100% Duty, II/O = 0 mA SCS1 < 0.2V, SCS2 > VCC - 0.2V VIN < 0.2V or VIN > VCC - 0.2V, Cycle Time = 1 s 100% Duty, II/O = 0 mA ISB Standby Current (TTL Input) SCS1 = VIH or SCS2 = VIL or SUB, SLB = VIH VIN = VIH or VIL SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V IOL = 2.1 mA IOH = -1.0 mA 2.4 Min -1 -1 Max 1 1 Unit A A
ICC ICC1
Operating Power Supply Current Average Operating Current
3 15
mA mA
2
mA
300
A
ISB1
Standby Current (CMOS Input)
10
A
VOL VOH
Output Low Output High
0.4
V V
Capacitance(1)
(Temp = 25 C, f = 1.0 MHz)
Symbol CIN COUT Note: Parameter Input Capacitance (Add, SCS1, SCS2, SLB, SUB, SWE, SOE) Output Capacitance (I/O) Condition VIN = 0 V VI/O = 0 V Max 8 10 Unit pF pF
1. These parameters are sampled and not 100% tested.
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
AC Characteristics
TA = -40 C to 85 C, Unless Otherwise Specified
70 ns # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol tRC tAA tACS tOE tBA tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tOH tWC tCW tAW tBW tAS tWP tWR tWHZ tDW tDH tOW Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid SLB, SUB Access Time Chip Select to Output in Low Z Output Enable to Output in Low Z SLB, SUB Enable to Output in Low Z Chip Deselection to Output in High Z Out Disable to Output in High Z SLB, SUB Disable to Output in High Z Output Hold from Address Change Write Cycle Time Chip Selection to End of Write Address Valid to End of Write SLB, SUB Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 10 5 10 0 0 0 10 30 30 30 30 0 30 0 0 20 0 5 20 25 25 25 Min 70 70 70 35 70 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC Test Conditions
TA = -40 C to 85 C, Unless Otherwise Specified
Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW Others Value 0.4V to 2.2V 5 ns 1.5V CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
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3338B-STKD-6/03
AC Test Loads
VTM = 2.8V
1029 Ohm DOUT CL
(1)
1728 Ohm
Note:
Including jig and scope capacitance.
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Timing Diagrams
Read Cycle 1(1),(4)
tRC ADDRESS tAA tACS SCS1 tOH
SCS2 tBA SUB, SLB tOE SOE tOLZ(3) tBLZ(3) DATA OUT HIGH-Z tCLZ(3) DATA VALID tOHZ (3) tBHZ(3) tCHZ(3)
Read Cycle 2(1),(2),(4)
tRC ADDRESS tAA tOH DATA OUT
PREVIOUS DATA DATA VALID
tOH
Read Cycle 3(1),(2),(4)
SCS1 SUB, SLB
SCS2
tACS tCLZ (3)
DATA VALID
tCHZ (3)
DATA OUT
Notes:
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active status. 2. SOE = VIL. 3. Transition is measured 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
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3338B-STKD-6/03
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tCW tWR(2)
SCS1
SCS2
tAW tBW
SUB, SLB
tWP
SWE
tAS tDW DATA VALID tWHZ(3)(7) tOW
(5) (5)
tDH
DATA IN
HIGH-Z
tAS
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
tAS tCW tWR(2)
SCS1
tAW
SCS2
tBW
SUB, SLB
tWP
SWE
tDW tDH HIGH-Z
DATA IN
DATA VALID HIGH-Z
DATA OUT
Notes:
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB. 2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after the SWE transition, outputs remain in a high impedance state. 5. Q (data out) is the same phase with the write data of this write cycle. 6. Q (data out) is the read data of the next address. 7. Transition is measured 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Data Retention Electric Characteristic
TA = -40 C to 85 C
Symbol VDR Parameter VCC for Data Retention Test Condition SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V Vcc=1.5V, SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V Min 1.2 Typ Max 3.3 Unit V
ICCDR
Data Retention Current
0.2
6
A
tCDR tR Notes:
Chip Deselect to Data Retention Time Operating Recovery Time
See Data Retention Timing Diagram
0 tRC
ns ns
1. Typical values are under the condition of TA = 25 C. Typical values are sampled and not 100% tested. 2. tRC is read cycle time.
Data Retention Timing Diagram 1
VCC 2.7V tCDR
DATA RETENTION MODE
tR
IH VDR
SCS1 > VCC - 0.2V
SCS1 VSS
Data Retention Timing Diagram 2
VCC 2.7V SCS2 VDR tCDR
DATA RETENTION MODE
tR
0.4V VSS
SCS2 < 0.2V
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3338B-STKD-6/03
8-megabit SRAM Description Features
The 8-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 512K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for high-speed and low-power circuit technology. It is particularly well-suited for the high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
* Fully Static Operation and Tri-state Output * TTL Compatible Inputs and Outputs * Battery Backup
- 1.2V (Min) Data Retention
Voltage (V) 2.7 - 3.3
Speed (ns) 70
Operation Current/ICC (mA) (Max) 3
Standby Current (A) (Max) 15
Temperature ( C) -40 - 85
Block Diagram
A0 ROW DECODER SENSE AMP I/O0
DATA I/O BUFFER
BLOCK DECODER
PRE DECODER
ADD INPUT BUFFER
I/O7 I/O8
MEMORY ARRAY 512K X 16 WRITE DRIVER
COLUMN DECODER
I/O15
A18
SCS1 SCS2 SOE SLB SUB SWE
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AT52BR3224A(T)/3228A(T)
Absolute Maximum Ratings(1)
Symbol VIN, VOUT VCC TA TSTG PD Note: Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Rating -0.3 to 3.6 -0.3 to 4.6 -40 to 85 -55 to 150 1.0 Unit V V C C W
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Truth Table
I/O Pin SCS1 H X
(1)
SCS2 X
SWE
SOE
SLB(2) X
SUB(2) X
Mode
I/O0 - I/O7
I/O8 - I/O15
Power
(1)
L X
X
X H L H H L L H L
Deselected
High-Z
High-Z
Standby
X
L(1)
H
H
H
H L L H
Output Disabled
High-Z
High-Z
Active
DIN High-Z Write DIN DIN
High-Z DIN DIN High-Z High-Z DOUT DOUT High-Z Active Active
L
H
L
X L L H L H L
DOUT High-Z Read DOUT DOUT
L
H
H
L L L
Notes:
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH) 2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8 - I/O15.
Recommended DC Operating Condition
Symbol VCC VSS VIH VIL
(1)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage
Min 2.7 0 2.2 -0.3
(1)
Typ 3.0 0
Max 3.3 0 VCC + 0.3 0.6
Unit V V V V
Note:
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
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3338B-STKD-6/03
DC Electrical Characteristics
TA = -40 C to 85 C
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition VSS < VIN < VCC VSS < VOUT < VCC, SCS1 = VIH or SCS2=VIL or SOE = VIH or SWE = VIL or SUB = VIH, SLB = VIH SCS1 = VIL, SCS2=VIH, VIN = VIH or VIL, II/O = 0 mA SCS1 = VIL, SCS2 = VIH, VIN = VIH or VIL, Cycle Time = Min 100% Duty, II/O = 0 mA SCS1 < 0.2V, SCS2 > VCC - 0.2V VIN < 0.2V or VIN > VCC - 0.2V, Cycle Time = 1 s 100% Duty, II/O = 0 mA ISB Standby Current (TTL Input) SCS1 = VIH or SCS2 = VIL or SUB, SLB = VIH VIN = VIH or VIL SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V IOL = 2.1 mA IOH = -1.0 mA 2.4 Min -1 -1 Max 1 1 Unit A A
ICC ICC1
Operating Power Supply Current Average Operating Current
3 15
mA mA
2
mA
0.3
mA
ISB1
Standby Current (CMOS Input)
15
A
VOL VOH
Output Low Output High
0.4
V V
Capacitance(1)
(Temp = 25 C, f = 1.0 MHz)
Symbol CIN COUT Note: Parameter Input Capacitance (Add, SCS1, SCS2, SLB, SUB, SWE, SOE) Output Capacitance (I/O) Condition VIN = 0 V VI/O = 0 V Max 8 10 Unit pF pF
1. These parameters are sampled and not 100% tested.
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AT52BR3224A(T)/3228A(T)
AC Characteristics
TA = -40 C to 85 C, Unless Otherwise Specified
70 ns # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol tRC tAA tACS tOE tBA tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tOH tWC tCW tAW tBW tAS tWP tWR tWHZ tDW tDH tOW Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid SLB, SUB Access Time Chip Select to Output in Low Z Output Enable to Output in Low Z SLB, SUB Enable to Output in Low Z Chip Deselection to Output in High Z Out Disable to Output in High Z SLB, SUB Disable to Output in High Z Output Hold from Address Change Write Cycle Time Chip Selection to End of Write Address Valid to End of Write SLB, SUB Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 10 5 10 0 0 0 10 70 60 60 60 0 50 0 0 30 0 5 20 25 25 25 Min 70 70 70 35 70 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC Test Conditions
TA = -40 C to 85 C, Unless Otherwise Specified
Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW Others Value 0.4V to 2.2V 5 ns 1.5V CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
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3338B-STKD-6/03
AC Test Loads
VTM = 2.8V
1029 Ohm DOUT CL
(1)
1728 Ohm
Note:
Including jig and scope capacitance.
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AT52BR3224A(T)/3228A(T)
Timing Diagrams
Read Cycle 1(1),(4)
tRC ADDRESS tAA tACS SCS1 tOH
SCS2 tBA SUB, SLB tOE SOE tOLZ(3) tBLZ(3) DATA OUT HIGH-Z tCLZ(3) DATA VALID tOHZ (3) tBHZ(3) tCHZ(3)
Read Cycle 2(1),(2),(4)
tRC ADDRESS tAA tOH DATA OUT
PREVIOUS DATA DATA VALID
tOH
Read Cycle 3(1),(2),(4)
SCS1 SUB, SLB
SCS2
tACS tCLZ (3)
DATA VALID
tCHZ (3)
DATA OUT
Notes:
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active status. 2. SOE = VIL. 3. Transition is measured 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
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Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tCW tWR(2)
SCS1
SCS2
tAW tBW
SUB, SLB
tWP
SWE
tAS tDW DATA VALID tWHZ(3)(7) tOW
(5) (5)
tDH
DATA IN
HIGH-Z
tAS
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
tAS tCW tWR(2)
SCS1
tAW
SCS2
tBW
SUB, SLB
tWP
SWE
tDW tDH HIGH-Z
DATA IN
DATA VALID HIGH-Z
DATA OUT
Notes:
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB. 2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after the SWE transition, outputs remain in a high impedance state. 5. Q (data out) is the same phase with the write data of this write cycle. 6. Q (data out) is the read data of the next address. 7. Transition is measured 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Data Retention Electric Characteristic
TA = -40 C to 85 C
Symbol VDR Parameter VCC for Data Retention Test Condition SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V Vcc = 3V, SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V See Data Retention Timing Diagram 0 tRC Min 1.2 Typ Max 3.3 Unit V
ICCDR
Data Retention Current
1
8
A
tCDR tR Notes:
Chip Deselect to Data Retention Time Operating Recovery Time
ns ns
1. Typical values are under the condition of TA = 25 C. Typical values are sampled and not 100% tested. 2. tRC is read cycle time.
Data Retention Timing Diagram 1
VCC 2.7V tCDR
DATA RETENTION MODE
tR
IH VDR
SCS1 > VCC - 0.2V
SCS1 VSS
Data Retention Timing Diagram 2
VCC 2.7V SCS2 VDR tCDR
DATA RETENTION MODE
tR
0.4V VSS
SCS2 < 0.2V
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Ordering Information
tACC (ns) 70 70 70 70 Ordering Code AT52BR3224A-70CI AT52BR3224AT-70CI AT52BR3228A-70CI AT52BR3228AT-70CI Flash Boot Block Bottom Top Bottom Top Flash Plane Architecture 32M - Single Bank 32M - Single Bank 32M - Single Bank 32M - Single Bank SRAM 256K x 16 256K x 16 512K x 16 512K x 16 Package 66C5 66C5 66C5 66C5 Operation Range Industrial (-40 to 85 C) Industrial (-40 to 85 C) Industrial (-40 to 85 C) Industrial (-40 to 85 C)
Package Type 66C5 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
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AT52BR3224A(T)/3228A(T)
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AT52BR3224A(T)/3228A(T)
Packaging Information
66C5 - CBGA
E
0.12 C C Seating Plane
Marked A1 Identifier D
Side View
Top View
A1 A
0.60 REF
E1 e A1 Ball Corner 1.20 REF
A B C D E F G H
D1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL e
12 11 10 9 8 7 6 5 4 3 2 1
MIN 9.90 - 7.90 - - 0.25
NOM 10.00 8.80 8.00 5.60 - - 0.80 BSC
MAX 10.10 - 8.10 - 1.20 -
NOTE
E E1 D
Ob
Bottom View
D1 A A1 e Ob
-
0.40
-
09/19/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 66C5 REV. A
R
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3338B-STKD-6/03
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